1. Field of the Invention
The present invention relates to semiconductor technology and in particular, to a semiconductor memory device and a fabrication method thereof.
2. Description of the Related Art
In the rapidly evolving integrated circuit industry, the developmental trend is toward high performance, miniaturization, and high operating speeds. Accordingly, dynamic random access memory (DRAM) fabrication methods have developed rapidly. In particular, increasing large memory capacity is important for DRAMs. Typically, DRAM cells include a transistor and a capacitor. With DRAM capacity reaching 512 MB, the size of memory cells and transistors have shrunk to meet demands for higher integration, higher memory capacity and higher operating speeds. For conventional planar capacitor technology however, relatively more useable surface area on an integrated circuit is required, thus making it difficult to meet the previously mentioned demands. Accordingly, three dimensional (3-D) technology, such as deep trench capacitor technology, has been applied to DRAM fabrication with the goal of reducing the area occupied by the transistor and the capacitor on the semiconductor substrate.
In three dimensional (3-D) memory fabrication, the silicon substrate between the trench capacitors serve as an active area for a transistor. In order to prevent the buried straps (BS), serving as a portion of the transistor drain region, from merging (i.e. BS merge), the neighboring trench capacitors must be separated by a suitable distance. The buried strap is formed by the thermal diffusion of high ion concentrations doped in a conductive layer in the memory cell into the substrate. This is called BS out-diffusion. If the diffusion area of the buried strap is excessive, the merging of buried straps between neighboring trenches may result, inducing short circuiting of the semiconductor memory device. Accordingly, it is difficult to further reduce the size of related devices for increasing device integration.